The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 1998

Filed:

Oct. 13, 1995
Applicant:
Inventors:

Koichi Hashimoto, Kawasaki, JP;

Takeshi Kamata, Kawasaki, JP;

Yukinobu Hikosaka, Kawasaki, JP;

Akihiro Hasegawa, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
216 67 ; 1566251 ; 1566431 ; 1566461 ; 1566591 ; 216 41 ; 216 68 ; 216 70 ; 427569 ; 427571 ; 427575 ; 438710 ; 438723 ; 438758 ;
Abstract

A method of manufacturing a semiconductor device including the steps of: (a) transporting a semiconductor wafer into a plasma process system, the semiconductor wafer having a semiconductor layer, a field insulating film and a gate insulating film formed on the semiconductor layer, said gate insulating film having a breakdown voltage of B (V) and a thickness of 10 nm or thinner, a conductive layer of a structured antenna formed on the gate insulating film and the field insulating film, the conductive layer having an antenna ratio of 500 or higher, and an insulating material pattern formed on the conductive layer, the insulating material pattern having an opening with an aspect ratio larger than 1; and (b) processing the semiconductor wafer in plasma having an electron temperature of Te (eV) equal to or less than B. With this method, it is possible to prevent damages to a gate insulating film even during a fine pattern process.


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