Multi-threaded cell for a memory

Abstract

A multi-threaded memory (and associated method) for use in a multi-threaded computer system in which plural threads are used with a single processor. The multi-threaded memory includes: multi-threaded storage cells; at least one write decoder supplying information to a selected multi-threaded storage cell; and at least one read decoder accessing information from a selected multi-threaded storage cell. Each of the multi-threaded storage cells includes: N storage elements, where N.gtoreq.2, each of the N storage elements having a thread-correspondent content; a write interface supplying information to the intra-cell storage elements; and a read interface reading information from the intra-cell storage elements. At least one of the intra-cell read and write interfaces selects one of the thread-correspondent contents based at least in part by identifying the corresponding thread to achieve intra-cell thread-correspondent content selection.