The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 1998
Filed:
Feb. 26, 1996
Paul Gordon Robertson, Austin, TX (US);
Other;
Abstract
A computer system and arbitrator prevent a livelock condition from occurring between a host bus bridge and a PCI bridge, where the host bus bridge and PCI bridge conform to the specification delineated in the PCI-to-PCI Bridge Architecture Specification 1.0 and PCI Local Bus Specification 2.0. The system includes an arbitrator for masking from the PCI bridge a request (REQ.sub.--) generated by a device on a second bus. The arbitrator requests that the host bus bridge flush all existing I/O requests (FLUSHREQ.sub.--) and postpone any future I/O requests from a central processing unit. The third step includes, in response to a notification from the host bus bridge that all I/O requests have been flushed and that any future I/O requests from the central processing unit will be postponed (MEMACK.sub.--), the arbitrator unmasks the request to the PCI bridge (GREQ.sub.--). In response to unmasking the request to the PCI bridge, the PCI bridge grants control of the second bus to the device (GNT.sub.--). This system guarantees that any data posted in an internal write buffer of the bus bridge can be delivered to system memory.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile