The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 1998
Filed:
Apr. 05, 1996
Hiromichi Ishibashi, Osaka-fu, JP;
Toshiyuki Shimada, Koubesi, JP;
Yasuaki Edahiro, Osaka-fu, JP;
Mitsurou Moriya, Naraken, JP;
Ryusuke Horibe, Koubesi, JP;
Hiroyuki Miyachi, Kyoto-fu, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
A phase error between an information signal including a reference signal that can be detected asynchronously and a synchronized signal that is synchronously produced from the information signal is detected, and a signal in response to an absolute value of the phase error is produced. Further, a defect detecting signal is produced in response to the absolute value of the phase error. Therefore, whether a pulse signal exceeding a maximum value of the pulse width of the information signal, that is, a pulse signal exceeding the pulse width of the reference signal, is detected or not, it is possible to detect that the signal reproduction enters a defect region immediately after the entry. Accordingly, a defect with noise or a track jumping can be detected rapidly. Furthermore, an information transition interval of the information signal is measured for a prescribed period of time, and the defect detecting signal is terminated in response to a measured value of a time length of the reference signal that is detected in the prescribed period of time, in other words, the passing of the signal reproduction through the defect region is detected with reference to the synchronization of the reference signal. Therefore, pseudo locking of a PLL is avoided when it is operated again, and the PLL can be accurately re-locked.