Semiconductor memory device capable of outputting multi-bit data using a

Abstract

A semiconductor memory device is disclosed which can read a plurality of bit units and which can suppress an increase in current consumption and in chip size even if the number of bits serving as a unit of reading is increased. The semiconductor memory device includes a memory cell array having memory cells arranged in a matrix form such that a plurality of columns are divided into a plurality of sections, a plurality of column selection circuits for selecting each of the columns of the memory cell array, a sense amplifier for sense-amplifying data transferred through the data lines, and a column selection control circuit for controlling the plurality of column selection circuits to select one of the plurality of sections of the memory cell array and one of the columns of the sections and to read bit data from the selected column, sequentially.