System and method for serial to parallel data conversion using delay line

Abstract

A serial data to parallel data converter is disclosed which has the advantage of accurately converting high frequency serial data to parallel data while using clock signals operating at a relatively low frequency. A low bit error rate is achieved by avoiding the use of multiple high speed clock lines typically found in other converters. The simplified circuit design also has the advantage of requiring minimal semiconductor layout area and reduced power requirements. One embodiment includes a buffer, a first data delay line, coupled to receive serial data from the buffer, and a phase lock loop (PLL), coupled to receive serial data from the buffer. A second data delay line is configured as a voltage controlled oscillator (VCO) within the PLL. The PLL locks onto the incoming serial data signal and provides a control signal back to the first data delay line to ensure it is storing serial data bits as they arrive. After n-bits of data have been transmitted the first data delay line contains a n-bit wide parallel word.