Differential to single ended conversion technique for an operational

Abstract

An operational amplifier having an input and an output stage. The input stage includes first and second source-coupled NMOS input transistors for accepting a differential input voltage and first and second PMOS load transistors for supplying current to each input transistor. A node between the first input transistor and first load transistor is coupled to a gate of a third PMOS transistor having its source coupled to a positive supply and its drain coupled to the sources of the input transistors and to a negative supply through a first biasing transistor. The output stage includes a fourth PMOS transistor having its gate coupled to a node between the second input transistor and the second load transistor and a source coupled to the positive supply voltage. A drain of the output transistor forms an output node and is coupled to the negative supply through a second biasing transistor. To minimize the input offset voltage, a ratio of the width-to-length of the third PMOS transistor to the width-to-length of the fourth PMOS transistor equals to a ratio of a quiescent drain current in the third PMOS transistor to a quiescent drain current in the fourth PMOS transistor. The load transistors have relatively large lengths for high gain while the third and fourth PMOS transistors have small lengths for high speed. Therefore, the operational amplifier has low input offset voltage, high speed and high gain.