The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 1998

Filed:

Sep. 28, 1995
Applicant:
Inventor:

Takashi Yajima, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257306 ; 257311 ; 257324 ; 257377 ;
Abstract

A novel structure of a semiconductor memory device on a silicon substrate comprising: a first area on which stacked capacitor memory cells comprising top and bottom electrodes sandwiching a dielectric film are formed; a second area including at least a contact hole in which at least a wiring layer is formed; and a plurality of inter-layer insulators extending over both the first and second areas, wherein: the a plurality of inter-layer insulators have two different total thickness between the first and second areas so that the total thickness on the first area is larger than that on the second area to thereby sufficiently reduce an aspect ratio of the at least a contact hole on the second area for allowing the wiring layer in the contact hole to have a good step coverage as well as allowing a top inter-layer insulator to have a gentle slope with a good step coverage at a boundary between the first and second areas.


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