The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 1998

Filed:

Apr. 21, 1995
Applicant:
Inventor:

Pradeep Kumar Dubey, White Plains, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
395381 ; 395382 ; 395383 ; 395582 ; 395584 ; 395460 ; 395461 ; 395462 ; 395463 ; 39580023 ; 364D / ; 711122 ; 711123 ; 711133 ; 711137 ;
Abstract

The computer processing unit of the present invention includes a new prefetch instruction, referred to as an STOUCH instruction, which provides the capability to encode compile-time speculations associated with the conditional branches between the time the prefetch request is initiated and the time the prefetched data is actually needed. As a result of this explicit communication of compile-time speculations to the run-time hardware, prefetched lines based on invalid speculations can be discarded earlier, whereas, prefetched lines based on valid speculations can be retained longer in the cache, leading to better cache performance.


Find Patent Forward Citations

Dubey, Pradeep. (1998). Method and apparatus for biasing cache lru for prefetched (U.S. Patent No. 5774685). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5774685

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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