The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 1998
Filed:
Oct. 08, 1996
Ralph Warren Haines, Atherton, CA (US);
Dan Craig O'Neill, San Carlos, CA (US);
Stephen C Pries, Grand Prairie, TX (US);
William V Miller, Arlington, TX (US);
Kent B Waterson, Everman, TX (US);
David S Weinman, Dallas, TX (US);
Michael J Shay, Arlington, TX (US);
Jianhua Helen Pang, Arlington, TX (US);
Daniel R Herrington, Burleson, TX (US);
Brian J Marley, San Jose, CA (US);
John R Gunther, Alvarado, TX (US);
Alexander Perez, Suunnyvale, CA (US);
James Andrew Colgan, Ichikawa, JP;
Robert James Divivier, San Jose, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
An integrated circuit (IC) includes multiple circuits and functions which share multiple internal signal buses, three physical and five logical, according to distributed bus access and control arbitration. The multiple internal signal buses are shared among three tiers of internal circuit functions: a central processing unit and a DMA controller; a DRAM controller and a bus interface unit; and peripheral interface circuits, such as PCMCIA and display controllers. Two of the physical buses correspond to two of the logical buses and are used for communications within the IC. The third physical bus corresponds to three of the logical buses and is used for communications between the IC and circuits external to the IC. Arbitration for accessing and controlling the various signal buses is distributed both within and among the three tiers of internal circuit functions. Maximum performance is thereby achieved from the circuit functions accessed most frequently, while still achieving high performance from those circuit functions accessed less frequently. The IC may provided with a processor core with features that support In-Circuit Emulation (ICE).