The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 1998

Filed:

May. 30, 1997
Applicant:
Inventor:

Hideto Matsuoka, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 211 ;
Abstract

In a semiconductor memory device, in a normal operation, data is written to selected four memory cells in accordance with external write data DQ0 to DQ3 applied to four data input/output terminals. In test mode, same data is commonly written to the selected four memory cells in accordance with write data DQ applied to one data input/output terminal. In the test mode operation, signal transmission between the remaining three data input/output terminals and the corresponding input buffer circuits is cut off by a CMOS logic gate provided therebetween and controlled in accordance with a test mode designating signal /TE.


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Matsuoka, Hideto. (1998). Semiconductor memory device capable of realizing stable test mode (U.S. Patent No. 5774472). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5774472

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