Initialization circuit for a semiconductor memory device

Abstract

An initialization circuit for a semiconductor memory device includes an initialization signal generator that generates an initialization signal in response to a specific sequence of reset control signals. A transfer unit activates a reset signal for resetting various circuits on the device in response to either the initialization signal or a conventional power-up initialization signal. Thus, the initialization signal generator provides reliable initialization even if the power-up detection circuit fails. External row and column address strobe signals serve as two reset control signals, while a mode selection signal serves as another reset control signal. The initialization signal is activated when the three reset control signals are activated in the proper sequence, then deactivated when one of the control signals is deactivated.