Semiconductor integrated circuit and layout designing method for the same

Abstract

Functional blocks and block external wiring are roughly laid out in a semiconductor integrated circuit. The positions of cells in the functional blocks, block internal wiring and the block external wiring are determined through calculation of delay time as a sum of block external delay time and block internal delay time, so that clock skew of each cell is within a limited range and the delay time is within a desired range. Wiring patterns are formed in accordance with the determined wiring. In determining the positions of the cells in the functional blocks and the block internal wiring, a template corresponding to a clock tree is formed, and the cells and the wires are laid out based on the clock tree structure on the template. Since the delay time can be adjusted, the respective cells of the respective functional blocks in one semiconductor integrated circuit or respective cells of respective semiconductor integrated circuits in one system can be synchronized one another. Since the layout of the semiconductor integrated circuit is designed by using a clock tree in a top-down fashion, the layout can be quickly designed without increasing an occupied area.