The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 1998

Filed:

Sep. 26, 1996
Applicant:
Inventors:

Yoshiro Aoki, Yokohama, JP;

Youichi Masuda, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G / ;
U.S. Cl.
CPC ...
345 87 ; 345904 ;
Abstract

An array substrate of an LCD device includes a glass substrate, an n.times.m number of pixel electrodes arrayed in a matrix form on the glass substrate, an n-number of scanning lines formed along rows of the pixel electrodes on the glass substrate, an m-number of signal lines formed along columns of the pixel electrodes on the glass substrate, switching elements formed on the glass substrate and located adjacent to intersections of the scanning lines and signal lines, each switching element supplying a video signal from the signal line to the pixel electrode in response to a scanning signal supplied from the scanning line, and a test supporting circuit for sensing potentials of the scanning lines. The test supporting circuit includes a test section comprising an n-number of testing thin film transistors whose gates are connected to the scanning lines and a test wiring section connected to source-drain paths of the testing thin film transistors thereby to detect the operation states of the testing thin film transistors corresponding to the gate potentials thereof. The test wiring section includes first and second test pads between which the source-drain paths of the testing thin film transistors are connected in parallel, a third test pad to which a test voltage is applied with the first test pad used as a reference, and a resistive element connected between the second and third test pads, the test voltage being divided according to a resistance ratio between the resistive element and the testing thin film transistors.


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