The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 1998

Filed:

Nov. 08, 1996
Applicant:
Inventors:

Leonard C Vercellotti, Pawleys Island, SC (US);

Stephen A Lane, Cockeysville, MD (US);

Assignee:

Northrop Grumman Corporation, Los Angeles, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B / ;
U.S. Cl.
CPC ...
327110 ; 327313 ; 327403 ; 327502 ;
Abstract

A semiconductor switch including a plurality of die assembled hybrid circuit packages. Each package includes a relatively large number of parallely connected semiconductor switch devices, more particularly metal oxide semiconductor field effect transistors (MOSFETs). An active snubber circuit is connected to the MOSFETs in order to remove the requirement for current sharing during circuit interruption where the MOSFETs turn-off. Each MOSFET package furthermore includes metallic arc barriers between MOSFETs to prevent an arc from propagating from one failed MOSFET to neighboring MOSFETs. Also all of the MOSFETs are turned on momentarily to extinguish arcs whenever the semiconductor switch is in an open or non-conducting condition and a current flow is detected. Clamping of the gate electrode drive bus of the MOSFETs is additionally provided to ensure fusing of gate bonding wires coupling the gate electrodes of the respective MOSFETs to the gate drive bus.


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