The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 1998

Filed:

Nov. 28, 1995
Applicant:
Inventors:

Takahiro Kumauchi, Hamura, JP;

Takashi Hashimoto, Ome, JP;

Osamu Kasahara, Yatsuo-machi, JP;

Satoshi Yamamoto, Ome, JP;

Yoichi Tamaki, Kokubunji, JP;

Takeo Shiba, Kodaira, JP;

Takashi Uchino, Kunitachi, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438234 ; 438482 ; 438584 ; 438564 ; 438680 ; 148D / ;
Abstract

A method of manufacturing an improved bipolar transistor or BiCMOS having a phosphorus-doped polysilicon emitter electrode is disclosed. The method comprises forming an emitter electrode wherein a phosphorus-doped amorphous silicon film is deposited at temperature not higher than 540.degree. C. and then subjected to low temperature annealing treatment at a temperature of 600.degree. C. to 750.degree. C., under which the amorphous silicon is converted to a polysilicon and the phosphorus present in the amorphous silicon film is diffused into a base region to form an emitter region, followed by high temperature/short time annealing treatment at a temperature of 900.degree. C. to 950.degree. C. so that an activation rate of an impurity in a boron-doped polysilicon base electrode or source-drain regions of MOS.cndot.FET is improved.


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