Integrated circuit memory devices having improved dual memory bank

Abstract

Integrated circuit memory devices having improved dual memory bank control include circuits therein for controlling at least one pair of memory banks (e.g., DRAM memory banks) using a single row address strobe (RAS) signal. Such memory devices include first and second banks of memory cells and a memory bank control circuit coupled thereto for selectively disposing the first and second banks of memory cells in active modes of operation during respective nonoverlapping time intervals, in response to first and second master clock signals. The first and second master clock signals are generated by a single master clock signal generator comprising a row address strobe buffer and a bank select buffer. The strobe buffer is responsive to a row address strobe signal and the bank select buffer is responsive to outputs from the strobe buffer and a bank select signal. The bank select buffer preferably generates the first and second master clock signals at first logic potentials (e.g., logic 1) during nonoverlapping time intervals and at second logic potentials (e.g., logic 0) during overlapping time intervals. In response to the master clock signals, the memory bank control circuit disposes the first bank of memory cells in an active mode of operation when the first master clock signal applied thereto has an amplitude equal to the first logic potential and disposes the second bank of memory cells in an active mode of operation when the second master clock signal applied thereto has an amplitude equal to the first logic potential.