The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 1998

Filed:

Mar. 06, 1997
Applicant:
Inventors:

Harufusa Kondoh, Hyogo, JP;

Hiromi Notani, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B / ;
U.S. Cl.
CPC ...
331 57 ; 331135 ;
Abstract

A current type inverter circuit used in a Current Type Ring Oscillator and a Voltage-Controlled oscillator operates at a high speed with a low power consumption. A reference power source 1 has one end connected to a power source VDD and the other source receiving a reference current Iref. A drain and a gate of an NMOS transistor Q1 of a current mirror circuit CM1, as an input part, receive an input current Iin. A drain of an NMOS transistor Q2 is connected to an node N1 of the other end side of the reference power source 1 as an output part. As an input part, a drain and a gate of an NMOS transistor Q3 of a current mirror circuit CM2 are connected to the node N1 while a drain of an NMOS transistor Q4 functions as an output part for outputting an output current Iout. The transistors are set so that all of the conditions TS1.gtoreq.1, TS2.gtoreq.1 and TS1.multidot.TS2>1 are satisfied where TS1 is a ratio of the size of the NMOS transistor Q2 to the size of the NMOS transistor Q1 and TS2 is a ratio of the size of the NMOS transistor Q4 to the size of the NMOS transistor Q3.


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