The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 1998

Filed:

Sep. 13, 1996
Applicant:
Inventors:

Hyo-Hoon Park, Daejeon, KR;

Kwang-Joon Kim, Yusong-ku, KR;

Kyung-Sook Hyun, Daejeon, KR;

O-Kyun Kwon, Daejeon, KR;

Seok-Ho Song, Daejeon, KR;

Byueng-Su Yoo, Daejeon, KR;

Hye-Yong Chu, Daejeon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01J / ;
U.S. Cl.
CPC ...
2502081 ; 250551 ;
Abstract

An improved parallel optical logic operator provides a path for light to pass through substrates in which a light source and an optical logic device are arranged. An optical logic device operates by transmission of light forwarded to a predetermined direction. This increases integration efficiency of the system by eliminating optical parts for changing the light path. A unit chip includes a laser array for generating a predetermined light in accordance with an electrical signal for a logic process, a laser array substrate on which via holes are formed for passing light, a microlens array for converting the light beam emitted from each laser device of the laser array into a parallel light beam for passing through the via hole, and an optical logic circuit array formed with a combination of an S-SEED which performs a logic function by transmission of the light signal through an optical window in S-SEED. A plurality of unit chips are laminated so that the light emitted from the laser device of one of the unit chips passes through an optical logic circuit of a corresponding unit chip and can be made incident on the optical logic circuit in the next unit chip through a via hole.


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