The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 1998

Filed:

Apr. 01, 1997
Applicant:
Inventor:

Hiroshi Akamatsu, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 224 ;
Abstract

A semiconductor integrated circuit device includes a test mode circuit for generating a fuse blow test mode activation signal according to a signal applied to a predetermined terminal, a pass/fail confirmation circuit including a fuse element and providing a signal of a logic level according to a conduction/non-conduction state of this fuse element when the fuse blow test mode activation signal from the test mode circuit is active, and an output conversion circuit for converting an output signal of the pass/fail confirmation circuit into a signal observable at a predetermined external terminal. The fuse element included in the pass/fail confirmation circuit is blown out by a laser only when the semiconductor integrated circuit device is determined to be an acceptable product at the test of the wafer level. After packaging, determination of whether there is a cut off failure in any internal fuse element can easily be made in non-destructive manner.


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