Ancillary data processing circuit for audio decoding system

Abstract

The invention provides an ancillary data processing circuit wherein a bit train of ancillary data having a varying data length is converted into another bit train in units of a byte of a rearwardly packed form to make changing of byte boundaries in following processing unnecessary. The ancillary data processing circuit includes a clock masking circuit including a first 3-bit counter which is reset to zero by a synchronism detection signal and counts a first clock signal, a second 3-bit counter which receives the count value of the first counter as a preset value thereof in response to an ancillary data start signal and counts down a second clock signal, a flip-flop which is initialized in response to the ancillary data start signal, reverses the level thereof in response to an overflow signal of the second counter and outputs a masking signal, and a masking circuit which calculates a combination logic of the masking signal and the second clock signal and outputs the second clock signal or the zero level as a third clock signal in response to the level of the masking signal, and an OR circuit which outputs a result of logical ORing of the first and third clock signals as a read clock signal.