Semiconductor memory with nand type memory cells having nor gate

Abstract

A semiconductor memory with NAND type memory cells includes word drive circuits and selecting circuits. The word drive circuits receive first row selection signals for selecting memory cell blocks connected in series and second row selection signals for selecting given memory cells in the memory cell blocks. The selecting circuits receive the first row selection signals and control gates of memory cell block selection transistors connected in series with the memory cell blocks. Each of the word drive circuits includes a switching speed delaying circuit which causes a switching speed of selecting the memory cell blocks through the first row selection signals to be slower than a switching speed of selecting the given memory cells through the second row selection signals. The switching speed delaying circuit may be realized by inserting a resistor in a drain of each of the memory cell block selection transistors in the NOR gates. The changes of grounding inter-connection potential due to the discharge of inter-connection and gate capacitances are prevented from causing erroneous operation.