Integrated circuit memory devices having metal straps to improve word

Abstract

Integrated circuit memory devices having metal straps include an array of memory devices arranged as a plurality of sub memory blocks (SMB) in a semiconductor substrate, and a plurality of sub word line drivers (SWD) disposed between adjacent sub memory blocks in the substrate. In particular, a plurality of first signal lines at a first metal level (M1) and extending in a first direction on the array are provided. The first signal lines are directly connected to a first sub word line driver at a face of the substrate. In addition, a plurality of second signal lines are provided at a first metal level (M1) and extend in a second direction, orthogonal to the first direction, from the first sub word line driver across at least one sub memory block SMB. At least one metal strap is also provided at a second metal level (M2), above the first metal level. The metal strap preferably crosses the plurality of first signal lines and extends from a first side of the first sub word line driver to a second opposing side of the first sub word line driver. Thus, it is unnecessary to provide the first signal lines at the second metal level or provide metal segments or islands to interconnect the first signal lines to metallization at the first metal level and to the first sub word line driver. Accordingly, the memory device of the present invention can be more highly integrated and less susceptible to defects caused by bridge 'shorts'.