The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 1998

Filed:

Nov. 08, 1996
Applicant:
Inventors:

Seung Jin Seo, Kyungdi-do, KR;

Kug Sang Lee, Suwon, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365 52 ; 365 63 ; 36523003 ;
Abstract

A memory module includes a plurality of memory devices, each memory device including a plurality of memory cell arrays, a plurality of data input/output lines, and a memory cell array select input line. The plurality of memory cell arrays are arranged as a plurality of blocks such that data transfer is enabled between a memory cell array in each block of the plurality of blocks and a respective data input/output line of the plurality of data input/output lines when a predetermined voltage is applied to the memory cell array select input line. The module includes a circuit substrate on which the plurality of memory devices is mounted, the circuit substrate including first and second voltage busses. Means are provided for selectively connecting the memory cell array select input lines of the plurality of memory devices to the first and second voltage busses such that a predetermined voltage is applied to the memory cell array select input lines of the plurality of devices and data transfer is enabled between a selected memory cell array in each block of each memory device and a respective data input/output line of the memory device. Preferably, the selected memory cell arrays are free of defective memory cells, and memory devices of the plurality of memory devices have defective cells in memory cell arrays other than the selected memory cell arrays.


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