The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 1998
Filed:
Jul. 15, 1996
Makoto Kakegawa, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A logical simulator that creates a logical simulation model that can equally distribute the load to each processing element and certainly suppress a decrease in a parallel processing efficiency due to each processing element waiting for its synchronous operation, thus increasing the speed of the logical simulation. The logical simulator includes a load measuring unit for measuring the load of each of processing elements at a logical simulation execution time, and a load data file for holding as load data the result measured by the load measuring unit. The model creating unit creates a logical simulation model with a small load bias of each of the processing elements at the logical simulation execution time, based on the measured result from the load measuring unit. The logical simulator is applicable to check for the correctness in design before fabricating digital equipment such as a digital computer formed of logical circuits.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile