Dot-matrix display for screen having multiple portions

Abstract

A dot-matrix display apparatus includes an address conversion/switch circuit which converts a system address of 16 bits outputted from a CPU into a write address in a manner that a most significant bit of the system address becomes a least significant bit of the write address and remaining bits of the system address are shifted upward one by one bit so as to become remaining bits of the write address. The upper 8 bits of the write address becomes a Y address for designating a row of a VRAM and the lower 8 bits of the write address becomes an X address for designating a column of the VRAM. Display data are written in the VRAM in a manner that display data for an upper half of a screen of an LCD and display data for a lower half thereof are in a row one after the other. When the display data are read from the VRAM in accordance with read addresses from a display address generating circuit, the display data are outputted in a manner that the display data for the screen upper half and the display data for the screen lower half are in a row one after the other. Therefore, on the screen of the LCD, images are displayed simultaneously on the upper half and the lower half.