The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 1998

Filed:

Aug. 02, 1996
Applicant:
Inventors:

Seok Won Cho, Chungcheongbuk-do, KR;

Jong Moon Choi, Seoul, KR;

Assignee:

LG Semicon Co., Ltd., Cheongju, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438159 ; 438302 ; 438585 ; 438163 ;
Abstract

A thin film transistor and a fabricating method for a thin film transistor is disclosed which may be suitable for memory cells of a static random access memory (SRAM) or other devices. A thin film transistor according to this invention may include an insulation substrate, a gate electrode formed to have a negative slope at one side thereof on the insulation substrate, an insulation film side wall formed at the other side of the gate electrode, a gate insulation film formed on the insulation substrate, gate electrode and side wall, a semiconductor layer formed on the gate insulation film, impurity diffusion regions selectively formed within the semiconductor layer over the gate electrode, the side wall and the insulation substrate on the other side of the gate electrode, and a channel region formed within the semiconductor layer at the side of the gate electrode having the negative slope. A method for fabricating a thin film transistor in accordance with this invention may include processes for forming a gate electrode on an insulation substrate, forming a side wall at a side of the gate electrode, etching the other side of the gate electrode selectively to have a negative slope, depositing a gate insulation film and a semiconductor layer successively on the overall surface, forming a source and a drain regions by an vertical ion injunction. Transistors having a negative slope at both sides of the gate electrode also are disclosed.


Find Patent Forward Citations

Cho, Seok. (1998). Fabricating method for a thin film transistor with a negatively sloped (U.S. Patent No. 5766988). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5766988

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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