System for triggering direct memory access transfer of data between

Abstract

Data is transferred from a host system to a subsystem connected to the host by a system bus in an efficient manner using one or more virtual first in first out (FIFO) registers in host memory and a corresponding set of virtual FIFOs located in the subsystem memory. A transmission controller controls the transfer of data from the host FIFOs to the subsystem FIFOs while the subsystem processor reads and processes data from the subsystem FIFO. By accumulating data in the host FIFOs before transfer to the subsystem, overhead associated with starting and stopping data transfers over the system bus is substantially reduced.