The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 1998
Filed:
Sep. 12, 1996
Wade A Walker, Austin, TX (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A reorder buffer including a speculative storage section and a retired storage section is provided. The speculative storage section stores speculative register states; while the retired storage section stores committed register states corresponding to the execution of instructions which have been retired. The dependency checking logic of the reorder buffer checks dependencies for operands of instructions being dispatched against both the speculative and retired storage sections. In this manner, a dependency is always detected within the reorder buffer. Therefore, no selection between a register file value and a value provided from the reorder buffer need be made. In fact, the register file may be eliminated from a microprocessor employing the reorder buffer. The retired storage section comprises a shiftable queue in one embodiment. The shiftable queue stores committed register states and indications of the architected registers corresponding to the committed register states. As new committed register states are moved into the retired storage section, committed register states are shifted within the shiftable queue such that the old committed register states corresponding to the architected registers updated by the new committed register states are discarded. The new committed register states are stored into the head of the queue. A dynamic assignment of storage locations to architected registers is maintained.