Multiple frequency memory array clocking scheme for reading and writing

Abstract

The present invention provides a clocking circuit for receiving a particular sized data word from a common input at a fixed frequency, writing the word to a number of individual memory cells in a storage device, reading another particular sized data word from the individual memory cells at a second particular frequency and presenting the data words to a common output at the second frequency. The storage device can be implemented as a memory array but is not limited to a memory array. The size of the words written to the storage device can be larger, smaller or the same as the size of the word read from the storage device. The present invention uses a multi-bit write counter to distribute a write timing signal at a particular frequency to a number of decoder and multiplexer blocks and a multi-bit read counter to distribute a read timing signal at a second particular frequency to a number of sense amplifier blocks.