Re-sampling circuit and modulator using same

Abstract

A re-sampling circuit includes a poly-phase finite impulse response (FIR) interpolator; a polynomial interpolator having a sample input connected to a sample output of the poly-phase FIR interpolator; and a numerically controlled oscillator (NCO) having an output partitioned into: Nc integer bits connected to a control input of the FIR interpolator, and Nf fractional bits connected to a control input of the polynomial interpolator. The circuit may also include a reference clock for generating a reference clock signal. The NCO preferably further comprises a sample clock generator for generating a sample clock signal based on the reference clock signal, and the FIR interpolator further has a sample clock input for receiving the sample clock signal from the sample clock generator. In addition, the polynomial interpolator also preferably has an input for clocking output samples therefrom that is connected to the reference clock so that output samples from the polynomial interpolator are clocked out based upon the reference clock signal. The re-sampling circuit may be used in a modulator, for example, also including one or more mixers.