The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 1998
Filed:
Aug. 30, 1996
Hamid Partovi, Sunnyvale, CA (US);
Robert C Burd, Santa Clara, CA (US);
Udin Salim, San Jose, CA (US);
Frederick Weber, San Jose, CA (US);
Luigi Di Gregorio, Sunnyvale, CA (US);
Donald A Draper, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an 'implicit' one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.