The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 1998
Filed:
Oct. 30, 1995
Mario A Cugini, Vista, CA (US);
International Faster Corporation, Vista, CA (US);
Abstract
A test interface between an electrical circuit to be tested and a test controller generally includes a plurality of translation pins, a plurality of grid boards and a connector to a controller. Each translation pin has a first end disposed for electrical contact with a point to be tested on the circuit to be tested and has a second end; the second ends collectively forming an output grid. Each grid board includes a plurality of grid contacts printed on a peripheral receiving edge perpendicular to the boards faces. The plurality of grid boards are disposed such that the grid contacts form a receiving grid congruent with the output grid such that individual ones of the second ends of the translation pins make electrical contact with individual ones of the grid contacts. In an exemplary embodiment, the grid boards are arranged in groupings, each grouping including a switching grid board, at least one receiving grid board and electrical connection between the buss contacts of the receiving grid board and a circuit on the switching grid board. According to another embodiment of the invention, the high-density interface is integrated into a low-density interface by disposition between the low-density output grid and the electrical circuit to be tested.