The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 1998
Filed:
Mar. 29, 1996
Kouichi Yamaguchi, Kokubu, JP;
Noriaki Hamada, Kokubu, JP;
Hideto Yonekura, Kokubu, JP;
Takeshi Kubota, Kokubu, JP;
Yasuyoshi Kunimatsu, Kokubu, JP;
Yasuhide Tami, Kokubu, JP;
Masahiko Higashi, Kokubu, JP;
Yohji Furukubo, Kokubu, JP;
Kyocera Corporation, Kyoto, JP;
Abstract
In a circuit board obtained by providing a metallized layer of wiring on the surface or interior of an insulation substrate, the insulation substrate is, for example, a multi-layer circuit board or a package for semiconductor element, the insutating substrate obtained from a sintered body having a linear expansion coefficient of 8 to 18 ppm/.degree. C. at 40.degree. to 400.degree. C. which is prepared by sintering a molded body containing 20 to 80% of a glass having a liner expansion coefficient of 6 to 18 ppm/.degree. C. at 40.degree. to 400.degree. C. and 80 to 20% of a filler having a linear expansion coefficient of at least 6 ppm/.degree. C. When the circuit board of the present invention is surface mounted on an outer electric circuit substrate such as a printed wiring board having a large linear expansion coefficient, the occurrence of stress due to a difference between the linear expansion coefficients of both is suppressed, and the circuit board and the outer electric circuit can be electrically connected accurately and firmly over a long period of time. Furthermore, a mounted structure of a circuit board having high reliability which can sufficiently dealt with the use of multiple pins due to large sizing of a semiconductor element can be realized. Furthermore, simultaneous sintering with the Cu metallized layer can be performed, and since the binder can be removed efficiently, the product is of high quality and is cheap.