The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 1998

Filed:

Jun. 07, 1995
Applicant:
Inventors:

Karl M Guttag, Sugar Land, TX (US);

Keith Balmer, Bedford, GB;

Robert J Gove, Plano, TX (US);

Christopher J Read, Houston, TX (US);

Jeremiah E Golston, Sugar Land, TX (US);

Sydney W Poland, Katy, TX (US);

Nicholas Ing-Simmons, Huntingdon, GB;

Philip Moyse, Bronham, GB;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
711147 ; 711148 ; 711152 ; 711153 ;
Abstract

A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. A base address instruction executing on any one of the processors generates the base address corresponding to that processor. The base address preferably is substituted for the contents of a base address register in an address unit including a set of base address registers, a set of index address registers and a full adder.


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