Logic translation method for increasing simulation emulation efficiency

Abstract

A method of speeding up computer simulation/emulation of circuit logic designs. The method converts an original circuit logic design (intended for hardware packaging) to a different circuit form before starting computer simulation/emulation. The converted circuit form provides the same simulation/emulation results as would have been obtained with the original logic circuit. The method operates with multi-phase logic designs comprised of gate circuits using multi-phase clocking of the type commonly packaged in semiconductor chips. The method converts such multi-phase logic designs into a single-phase circuit form, which is presented to the computer for simulation/emulation that provides the same results as the multi-phase logic design but at a much faster speed. The method is presented with a multi-phase logic design containing flip-flops as the internal storage circuits. The method effectively retains the storage circuits found in a multi-phase logic design and replicates its logic blocks providing multiple phase outputs. Then the storage circuits are reconnected to the original and replicated logic blocks in a manner that enables a single clock cycle to operate the converted logic design to simulate/emulate the same results in the storage circuits, as if the original multi-phase logic design were being simulated or emulated, but at a much faster speed.