Method and apparatus for optimizing signed and unsigned load processing

Abstract

A method and apparatus for improving the performance of pipelined computer processors having fast clock speeds and processing cycles for performing signed and unsigned load operations to memory. A load instruction includes signed and unsigned variants. Signed load operations include accessing signed load data from memory, aligning and sign extending the value of the accessed data. The present invention provides two different schemes for scheduling the processor's pipelines to handle accessing signed and unsigned data from memory. The two schemes include a data dependent scheme that accesses data from memory where the sign of a load data is not known until the data has been accessed from memory, and an opcode dependent scheme when the sign value of data being accessed is known prior to accessing memory. In the data dependent scheme, the processor is scheduled to process a signed LOAD in two cycles if the load data is negative, and one cycle if the data is positive. In the opcode dependent scheme, signed load instructions are scheduled to execute in the processor's pipeline�s! in two cycles regardless of whether the data fetched from memory is negative or positive. The present invention further includes a delay return scheme in which the processor is able to process multiple consecutive load instructions by transitioning into a scheduling mode of handling all loads as signed.