The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 1998

Filed:

Oct. 20, 1995
Applicant:
Inventors:

William R Foland, Jr, Littleton, CO (US);

Richard T Behrens, Louisville, CO (US);

Alan J Armstrong, Longmont, CO (US);

Neal Glover, Broomfield, CO (US);

Assignee:

Cirrus Logic, Inc., Fremont, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
371 212 ; 371-51 ; 360 53 ; 360 31 ; 360 48 ;
Abstract

A measurement circuit is provided to obtain data for monitoring the quality of performance from a digital read channel. Elements of the digital read channel including a sequence detector are incorporated into an integrated circuit together with the measurement circuit. The measurement circuit relates digitized samples of readback data from a magnetic storage device to surrounding samples so that particular samples can be collected in accordance with their surroundings. The circuit includes a programmable time window which can be repeatedly opened for data collection. The circuit is designed to collect various types of data including the bit error rate, sample value, squared sample error, squared gain error, squared timing error, and the occurrences of sample error when it is outside an acceptable programmable threshold. The measurement circuit includes a signal generator for producing a test pattern that is first stored and then read to produce the digitized readback sample values. The measurement circuit also includes a conversion circuit for converting the test pattern to a sequence of expected sample values in accordance with a state machine model of the sequence detector. The sample value error results from a comparison of the readback sample value to the expected sample value.


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