Expansible high speed digital multiplexer

Abstract

A multiplexer, preferably on an integrated circuit chip, receives a plurality of buses each having a plurality of lines responsive to binary indications and passes the binary indications in the lines of a particular one of the buses. The multiplexer includes a plurality of circuit blocks each responsive to the binary indications in the lines of an individual one of the buses. Each block has a plurality of recursive circuits each having first and second stages. The second stages of the recursive circuits in an individual one of the circuit blocks receive an individual one of a plurality of control indications at a first side of the block to activate the first stages in such recursive circuits. The first stage in each recursive circuit in each individual circuit block receives at a second side of the block the binary indications in an individual line in an individual one of the buses to obtain a signal from such first stage in accordance with such binary indication upon the activation of such first stage. The output lines of the same binary significance in the different circuit blocks are connected in an OR relationship. Each output circuit in a plurality is responsive to the signals in the OR relationship of an individual binary significance from the recursive circuit in the activated block to provide output signals from the multiplexer. The multiplexer accordingly provides a recursive and expansible, arrangement for passing signals at each instant from a selected bus without any wire crossovers.