The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 1998
Filed:
Dec. 16, 1996
James D Allan, Colorado Springs, CO (US);
Robert W Manning, Monument, CO (US);
Cypress Semiconductor Corp., San Jose, CA (US);
Abstract
A block selecting scheme for a memory device. The block selecting scheme includes a sub word line driver circuit having multiple sub word line drivers and an inverter circuit. For one embodiment, the sub word line driver circuit includes four sub word line drivers. Each sub word line driver is used to select the sub word line for a corresponding memory block. Each of the sub word line drivers is coupled to a global word line via the inverter circuit. Furthermore, each of the sub word line drivers operates as an inverter. By coupling the global word line and each of the sub word lines via two inversion circuits, the global word line and the sub word lines are typically at the same voltage level. Thus, the deleterious effect of shorting between adjacent global word lines and sub word lines is substantially reduced. Furthermore, by grouping more than two sub word line drivers together, the overall die size of the memory device may be reduced.