The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 1998

Filed:

Aug. 01, 1997
Applicant:
Inventors:

Ying-Tsong Loh, Saratoga, CA (US);

Lily Ding, Fremont, CA (US);

Assignee:

VLSI Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438305 ; 438231 ; 438291 ; 438303 ; 438217 ;
Abstract

A technique for forming a high-performance sub-half micron MOS transistor is disclosed which has improved short channel characteristics without degradation of device performance. The transistor comprises a semiconductor substrate, a gate electrode, graded source and drain impurity regions, a first set of gate sidewall spacers, and a second set of gate sidewall spacers. The graded source and drain impurity regions comprise a relatively linear continuum of doped regions, ranging from lightly doped (LDD) regions, to moderately doped (MDD) regions, to heavily doped regions. Additionally, the transistor may include a punch through barrier region located within the substrate under the gate electrode. With these features, the transistor of the present invention allows for more precise control of conduction channel length without degradation of either (1) body factor and current drive, and/or (2) junction leakage, and without compromising hot carrier immunity.


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