The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 1998

Filed:

Sep. 28, 1994
Applicant:
Inventors:

Ramesh Chandra Agarwal, Yorktown Heights, NY (US);

Randall Dean Groves, Austin, TX (US);

Fred Gehrung Gustavson, Briarcliff Manor, NY (US);

Mark Alan Johnson, Austin, TX (US);

Brett Olsson, Round Rock, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395800 ; 375375 ; 364230 ; 3642319 ; 3642613 ; 364D / ;
Abstract

A single-instruction, multiple-data (SIMD) execution unit for use in conjunction with a superscalar data processing system is provided. The SIMD execution unit is coupled to a branch execution unit within a superscalar processor. The branch execution unit fetches instructions from memory and dispatches vector processing instructions to the SIMD execution unit via the instruction bus. The SIMD execution unit includes a control unit and a plurality of processing elements for performing arithmetic operations. The processing elements further include a register file having multiple registers and an arithmetic logic unit coupled to the register file. The arithmetic logic unit may include a fixed-point unit for performing fixed-point vector calculations and a floating-point unit for performing floating-point vector calculations. Once the control unit within the SIMD execution unit receives a vector instruction, the control unit translates the instruction into commands for execution by selected processing elements within the SIMD execution unit. If such a vector instruction requires access to memory, a fixed point execution unit within the superscalar processor may be utilized to calculate a memory address which is then utilized by the SIMD execution unit to access memory.


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