The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 1998

Filed:

Feb. 07, 1997
Applicant:
Inventors:

Kenneth C Yeager, Sunnyvale, CA (US);

Mazin S Khurshid, San Jose, CA (US);

Assignee:

Silicon Graphics, Inc., Mt. View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395393 ;
Abstract

Redundant mapping tables for use in processors that rename registers and perform branch prediction is presented. The redundant mapping tables include a plurality of primary RAM cells coupled to a plurality of redundant RAM cells. In the event of a branch instruction, the redundant RAM cells can save the contents of the primary RAM cells in a single clock cycle before the processor decodes and executes subsequent instructions along a predicted branch path. Should the branch instruction be mispredicted, the redundant cells can restore the primary RAM cells in a single clock cycle. A branch stack, coupled to the redundant mapping tables, updates restored mapping tables with changes made for preceding instructions that were decoded in parallel with the branch instruction. A plurality of levels of redundant RAM cells may be used to enable the nesting of a plurality of branch predictions at any one time.


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