Jitter suppression circuit for clock signals used for sending data from

Abstract

A jitter suppression circuit for a synchronous transmission network has a write clock generator for carrying out positive or negative stuffing, a buffer memory for storing data related to the main signals, a byte-bit converter, a clock mask, an N-phase clock generator, a read clock generator, and a smoothing unit. The byte-bit converter has an accumulator for accumulating bits related to the positive or negative stuffing according to the byte stuffing signal and a distributor for distributing the accumulated bits according to a moving average for a predetermined period, to generate smoothed bit stuffing signals. The clock mask masks clock signals corresponding to overhead bytes among the received clock signals. The N-phase clock generator divides the period of the output clock signal of the clock mask by N, to generate N-phase clock signals. The read clock generator sequentially selects the N-phase clock signals according to the bit stuffing signals, to generate clock signals for reading the buffer memory. The smoothing unit reads the data stored in the buffer memory according to the clock signals generated by the read clock generator while smoothing the masked clock signals corresponding to the overhead signals, and saves the smoothed read data for an asynchronous transmission network.