The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 1998

Filed:

Jan. 17, 1997
Applicant:
Inventor:

Frank William Angelotti, Rochester, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 271 ;
Abstract

Methods for testing interconnections on an electronic assembly include the steps of dynamically generating an interconnect topology model from one system, generating test patterns to test the interconnections, applying the test patterns to the boundary scan cells of the system under test to test the interconnections, and determining whether the interconnections match the interconnect topology model. The invention thus dynamically generates an interconnect topology model from a known working system, rather than deriving the interconnect topology model from design data that describes all the interconnections on an electronic assembly.


Find Patent Forward Citations

Angelotti, Frank. (1998). Method for testing interconnections between integrated circuits using a (U.S. Patent No. 5757820). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5757820

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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