Baseline correction circuit for pulse width modulated data readback

Abstract

A baseline correction circuit (BCC) compensates for the offset present on a pulse width modulated (PWM) signal in an optical readback system when associated transients first appear in the PWM signal, then compensates for the decay in the PWM signal so that significant baseline variations are minimized. The BCC includes a BCC switch coupled to switch the PWM signal responsive to a control unit and a low pass filter coupled through the BCC switch to receive the PWM signal. The low pass filter includes a capacitor coupled between the PWM signal and a ground reference, which stores the voltage of the baseline variation. A difference amplifier is connected to receive the low pass filtered output and also the PWM signal, and to provide a difference signal responsive to the difference between these two signals. The resultant signal is a high-pass filtered version of the PWM signal originally supplied to the BCC. A control unit monitors and controls disk operations, and supplies a transient event signal indicative of a predetermined upcoming baseline variation in the PWM signal, which turns on the BCC switch. At a predetermined time after the transient event has occurred and the baseline voltage has been stored on the capacitor in the low pass filter, the control unit switches off the BCC switch, and the signal from the low pass filter decays at a rate approximately following the input PWM signal into the BCC.