Microprocessor system with cache memory for eliminating unnecessary

Abstract

In a cache memory control apparatus, a cache hit ratio of a cache memory is increased by employing both of control information (cacheable or non-cacheable) and condition information (invalidation or validation) to avoid unnecessary invalidation of the cache data. The microprocessor system with a cache memory control apparatus includes a microprocessor for processing various data. A main memory unit stores main data in a designated physical address allocated by a page unit. An auxiliary memory unit stores auxiliary data in a designated physical address allocated by a page unit. A cache memory temporarily stores a portion of the main data to be stored in the main memory unit. A virtual memory space manages by a virtual address to transfer the main data between the microprocessor and the main memory unit through the cache memory and also to transfer the auxiliary data between the microprocessor and the auxiliary memory units. A virtual memory control unit controls the virtual memory space and outputs an indicating information of cacheable or non-cacheable. A register stores a mode value which is given from the microprocessor to discriminate data from the microprocessor to be stored in the main memory unit or in the auxiliary memory units. A cache memory control unit lets the cache memory be cacheable or non-cacheable based upon the indicating information from the virtual memory control unit and, in a case of non-cacheable and the mode value discriminating the data from the microprocessor to be stored in the auxiliary memory units, lets the microprocessor directly access the auxiliary memory units and lets the cache memory keep valid.