Clock signal regenerating circuit

Abstract

A clock signal regenerating circuit is provided for use in a receiver for receiving a burst signal or packet signal which is intermittently transmitted in digital radio communications, wherein a regenerated clock signal can be synchronized with a received signal having a short preamble. An edge extracting unit extracts an edge of the received signal and thereby detects synchronization timing involved in the received signal. A reference signal generating unit previously generates a plurality of quasi-reference signals having respective different phases and an identical frequency, and a selecting/outputting unit selects a quasi-reference signal having a phase closest to the synchronization timing involved in the received signal from among the quasi-reference signals, and outputs the selected signal as a clock signal for the receiver. Thus, the clock signal is not gradually synchronized with the synchronization timing involved in the received signal, but can be immediately synchronized with timing relatively close to the synchronization timing.