Jitter circuit for reduced switching noise

Abstract

A circuit for reducing switching noise caused by harmonics of an output coupled to a band of interest in a mixed signal communication device, with the mixed signal communication device having a predetermined sampling clock. The circuit comprises a bandpass delta-sigma modulator for receiving an input centered at intermediate frequency ('IF') to generate a digital output, In-phase and Quadrature-phase digital mixers for mixing the digital output from the bandpass delta-sigma modulator down to baseband digital signals, first and second digital integrators coupled to the digital mixers for integrating the baseband digital signals to generate integration outputs, first and second decimation latches coupled to the digital integrators for generating latched integration output, a programmable counter for generating jitter sampling clocks based on the predetermined sampling clock, where the jitter sampling clock has a fixed average sampling rate, first and second FIR engines coupled to the decimation latches for differentiating, low-pass filtering and droop-correcting the latched integration outputs, using the jitter sampling clocks to generate first and second filtered digital outputs.