The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 1998

Filed:

Jun. 14, 1996
Applicant:
Inventor:

Inh-seok Suh, Suwon, KR;

Assignee:

Samsung Aerospace Industries, Ltd., Kyongsangnam-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
327279 ; 327265 ; 327263 ;
Abstract

A digital signal delay circuit includes a first pair of counters for setting a starting point of a digital output signal by counting an adjustably set number of clock pulses corresponding to an intended time delay from a starting point of a digital input signal. The circuit further includes a second pair of counters for setting an ending point of the digital output signal by counting an adjustably set number of clock pulses corresponding to an intended output pulse width from an ending point of the digital input signal. The state of the digital output signal is only determined by the state of the output signal of the last counter in the first pair of counters. The output signal from the last counter in the first pair of counters controls a count starting point of the first counter in the second pair of counters. The output signal from the second pair of counters controls an initializing point on which the state of the output signal from the last counter in the first pair of counters is inverted.


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